Engineer's Folder
Array Architecture is a plug-and-play Compute-In-Memory arithmetic core that colocalizes logic and memory in a regular grid. Built on standard CMOS without changing the fabrication process, it can achieve an +85% efficiency gain over baselines and increase Bitcoin mining profitability by 75-100%. However, our long-term strategy is to license the underlying architecture across multiple semiconductor markets rather than focus on any single application family or industry. Mining and AI/LLM specific cores are our first choice because of market opportunities. We exist to make this architecture the default. For AI, cryptography, edge devices, Bitcoin mining. For every workload that saturates on arithmetic throughput and memory bandwidth. We will license the IP, prove it in silicon, and partner with the fabs and design houses that are ready to leave the carry-over chain behind.
Presentation
Technical Overview
30-Minute presentation of the bottleneck problem in processors, the Compute-In-Memory problem, and the solution offered by our IP family. This presentation goes into very little technical detail.
Document
Technical Detail
We provide a 14-page walk-through of our architecture, bridging the addition algorithm to the circuit logic that executes the operation. This is the document to read if you want to understand how the patent works and why the proposed arithmetic core has the characteristics and properties it has.
Document
Patent Description
We include a copy of the original international patent application filed through the USPTO, under the PCT.
Document
References and
Supporting Data
This document provides supporting data to all the technical claims and projections, with full bibliography for claims regarding Compute-In-Memory, computing throughput, hash rates, energy costs, data sources, market sizes, and financial projections used in our analysis. This document provides data to back claims, data tables and projections included in our analysis. Each section includes sources, bibliography and formulas.
Document
16-Month ASIC
Development Plan
This document is a detailed 16-month plan to prototype a CIM arithmetic core in an industry-grade pre-silicon GDSII Stream File, and implementation into a fully functional System-On-Chip design. This document includes an overview of the tech team we seek to build, the tools and resources we require to execute, our planned workflow and a detailed 24 month operating budget.
Spreadsheet
Timeline
This detailed timeline shows the parallelization of the main administrative and technical tasks and subtasks our three-phase development plan requires in order to be executed on-time and on-budget. We provide a week-by-week breakdown of activities going from contacting talent acquisition agencies, to foundry-ready GDSII Files.
References for Technical Analysis
The energy and performance inefficiencies addressed by this patent are not new. They are the direct consequence of the Von Neumann Bottleneck, a fundamental limitation of the stored-program computer architecture that has been recognized and studied for decades. The cost of moving data is orders of magnitude higher than the cost of computing. This was established in seminal research and has been a central focus of computer architecture for several decades. The references cited below include landmark surveys, long-standing comparative analysis, and foundational studies that have stood the test of time, precisely because they correctly identified this primary obstacle to efficiency.
General Computer Architecture
Computer Architecture: A Quantitative Approach
John L. Hennessy and David A. Patterson, 6th ed. (Cambridge, MA: Morgan Kaufmann, 2018).
CMOS VLSI Design: A Circuits and Systems Perspective
Neil H. E. Weste and David M. Harris, published by Addison-Wesley in 2015.
Researchers use 2D material to reshape 3D electronics for AI hardware
3D-Stacked CMOS Takes Moore’s Law to New Heights
A Little Bit of Everything. Code, Assembly, Arithmetic, Registers.
Arithmetic Logic Units (ALUs)
Notes on Computer Organization: Computer Arithmetic
Advanced Arithmetic Techniques
Performance Comparison of Asynchronous Adders
Franklin, Mark A. and Pan, Tienyo. Report Number: WUCS-94-24 (1994). All Computer Science and Engineering Research.
Performance Analysis of Fast Adders Using VHDL
R.P.P. Singh, Parveen Kumar and Balwinder Singh. 2009 International Conference on Advances in Recent Technologies in Communication and Computing. IEEE Computer Society. DOI: 10.1109/ARTCom.2009.132.
Area, Delay and Power Comparison of Adder Topologies
R. UMA, Vidya Vijayan, M. Mohanapriya, Sharon Paul. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012.
Performance Comparison of Some Synchronous Adders
P. Balasubramanian. Technical Note, School of Computer Science and Engineering, Nanyang Technological University, Singapore, October 2018. Available at: arXiv:1810.01115 [cs.AR]. DOI: 10.48550/arXiv.1810.01115.
Fast Multiplication: Algorithms and Implementation
Gary W. Bewick. STANFORD UNIVERSITY, February 1994. http://i.stanford.edu/pub/cstr/reports/csl/tr/94/617/CSL-TR-94-617.pdf
Design of 16-Bit Low-Power ALU-DBGPU
Rengasamy, Dr. Dhanabal & Bharathi, Venuturla & Salim, Saira & Thomas, Bincy & Soman, Hyma & Sahoo, Sarat Kumar. (2013). Intern. J. Eng. Technol.. 5. 2172-2180.
Design of Multiplication and Division Operation for 16 Bit Arithmetic Logic Unit (ALU)
Mahamad, Abd Kadir, Muhammad Ikmal Mohd Taib, Muhammad Najmi Zikry Nazri, Syazana Khairol Amali, and Muhamad Amirul Mohd Yusof @Md Jusoh1. 2020. Journal of Electronic Voltage and Application 1 (2): 46-54. https://publisher.uthm.edu.my/ojs/index.php/jeva/article/view/7219
An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm
Abrar, M., Elahi, H., Ahmad, B.A. et al. SN Appl. Sci. 1, 1348 (2019). https://doi.org/10.1007/s42452-019-1367-6
High Precision Integer Multiplication with a GPU Using Strassen’s Algorithm with Multiple FFT Sizes
N. Emmart and C. C. Weems, Parallel Processing Letters, Vol. 21, No. 03, pp. 359-375 (2011).
An Optimized Floating-Point Matrix Multiplication on FPGA
Zhang, Ting & Xu, Chengzhong & Li, Tao & Qin, Yunchuan & Nie, Min. (2013). Information Technology Journal. 12. 1832-1838. 10.3923/itj.2013.1832.1838.
Ping Xiang, Yi Yang, Huiyang Zhou, et. al. 2013. Proceedings of the 27th international ACM conference on International conference on supercomputing (ICS '13). Association for Computing Machinery, New York, NY, USA, 433–442.
Von Neumann Bottleneck
Computing's Energy Problem (and what we can do about it)
M. Horowitz, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014, pp. 10-14, DOI: 10.1109/ISSCC.2014.6757323.
Quantifying the Energy Cost of Data Movement in Scientific Applications
G. Kestor, R. Gioiosa, D. J. Kerbyson and A. Hoisie, 2013 IEEE International Symposium on Workload Characterization (IISWC), Portland, OR, USA, 2013, pp. 56-65, doi: 10.1109/IISWC.2013.6704670.
Accelerating Dependent Cache Misses with an Enhanced Memory Controller
Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt, The 43rd ACM/IEEE International Symposium on Computer Architecture (ISCA) , June 2016.
Why Haven’t CPU Clock Speeds Increased in the Last Few Years?
https://www.comsol.com/blogs/havent-cpu-clock-speeds-increased-last-years/
ASICs
Jim Keller’s Tenstorrent Wants To Compete With NVIDIA’s AI GPUs Using RISC-V Based AI CPUs
ASIC Design for Bitcoin Mining
Y. Sun, H. Yang, W. Zhang, and Y. Gu, University of Michigan, Ann Arbor, MI, USA, EECS 570 Final Report 2021. https://zwtaoumich.github.io/paper/EECS570_Final_Report.pdf
From Concept to Chip: The Art and Science of ASIC Design in Bitcoin Mining
https://d-central.tech/from-concept-to-chip-the-art-and-science-of-asic-design-in-bitcoin-mining/
Custom ASIC Design for SHA-256 Using Open-Source Tools
Franck, Lucas Daudt, Gabriel Augusto Ginja, João Paulo Carmo, José A. Afonso, and Maximiliam Luppe. 2024. Computers 13, no. 1: 9. https://doi.org/10.3390/computers13010009
Compute-In-Memory
New Computing Hardware Needs a Theoretical Basis
A Full Spectrum of Computing-In-Memory Technologies
Zhong Sun, Shahar Kvatinsky, Xin Si, Adnan Mehonic, Yimao Cai and Ru Huang. Institute for Artificial Intelligence, School of Integrated Circuits, Peking University, Beijing Advanced Innovation Center for Integrated Circuits, Beijing 100871, China.
Research Progress in Architecture and Application of RRAM with Computing-In-Memory
Chenyu Wang, Ge Shi, Fei Qiao, Rubin Lin, Shien Wu, Zenan Hu, Nanoscale Advances, Volume 5, Issue 6, 2023, Pages 1559-1573, ISSN 2516-0230. https://www.sciencedirect.com/science/article/pii/S2516023023023742
A Survey of Accelerator Architectures for Deep Neural Networks
Yiran Chen, Yuan Xie, Linghao Song, Fan Chen, Tianqi Tang. Engineering, Volume 6, Issue 3, 2020, Pages 264-274, ISSN 2095-8099.
Recent Developments in Low-Power AI Accelerators: A Survey
Åleskog, Christoffer, Håkan Grahn, and Anton Borg. 2022. Algorithms 15, no. 11: 419. https://doi.org/10.3390/a15110419
Hardware Accelerators for Artificial Intelligence
S M Mojahidul Ahsan, Anurag Dhungel, Mrittika Chowdhury, Md Sakib Hasan, Tamzidul Hoque. Available at arXiv:2411.13717 [cs.AR] (or arXiv:2411.13717v2 [cs.AR] for this version)
Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie. 2016. In Proceedings of the 43rd International Symposium on Computer Architecture (ISCA '16). IEEE Press, 27–39. https://doi.org/10.1109/ISCA.2016.13
China Makes Breakthrough in System-Integrated Memristor Computing-In-Memory Chips
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
Y. -H. Chen, T. Krishna, J. S. Emer and V. Sze, in IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 127-138, Jan. 2017,
doi: 10.1109/JSSC.2016.2616357.
Microchip Breakthrough May Reshape the Future of AI
Defense One.
Intel Invests in ‘Groundbreaking’ AI Chip Architecture Startup
Swiss Researchers Develop First Large-Scale In-Memory Processor
The Uncertain Future of In-Memory Compute
Semiconductor Engineering.
In-Memory Computing Challenges Come Into Focus
Semiconductor Engineering.
Cerebras
Beyond Quantum: MemComputing ASICs Could Shatter 2048-bit RSA Encryption
Security Week.